In system diagnostics through scan matrix

A method of in-system diagnostics through scan matrix, for use with an integrated circuit chip operable in a plurality of boundary scan test modes in which at least a part of the circuitry in the integrated circuit ship is tested, the method comprising the steps of:

• using an on-chip scan matrix controller to partition the circuitry in the integrated circuit chip into multiple matrix regions, with each of the matrix regions having a plurality of scan elements;
• using an on-chip instruction register to hold instructions for the scan matrix controller to partition said chip into said multiple matrix regions;
• and
• further using the on-chip scan matrix controller to test each of matrices for faults, according to instructions in the instruction register, by applying a test signal to the tested part of the circuitry.

An article of manufacture, for use with an integrated circuit chip operable in a plurality of boundary scan test modes in which at least a part of the circuitry in the integrated circuit ship is tested, the article of manufacture comprising:

• at least one computer usable medium having computer readable program code to execute a machine instruction in a processing unit, said computer readable program code executable by the processing unit to perform method steps for in-system diagnostics through scan matrix, said method steps comprising:
• using an on-chip scan matrix controller to partition the circuitry in the integrated circuit chip into multiple matrix regions, with each of the matrix regions having a plurality of scan elements;
• using an on-chip instruction register to hold instructions for the scan matrix controller to partition said chip into said multiple matrix regions;
• and
• further using the on-chip scan matrix controller to test each of matrices for faults, according to instructions in the instruction register, by applying a test signal to the tested part of the circuitry.