Method and apparatus for memory ac timing measurement
AssigneeFaraday Technology Corp.
InventorsChih-Chiang Hsu, Shang-Chih Hsieh
Life of this patent
Estimating the term…
Abstract
A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.
Claims13
A memory chip, comprising:
- a memory subsystem, for storing data, and comprising a plurality of pins;
- a clock tree, for balanceably sending a test signal source;
- and
- a timing measurement circuit, for receiving the test signal source sent out by the clock tree and delaying the test signal source individually to generate a plurality of delayed test signals, and sending the delayed test signals to the pins of the memory subsystem, so as to test memory AC timing parameters of the memory subsystem by adjusting the timing of the delayed test signals.
A timing measurement circuit of a memory chip, wherein the memory chip comprises a memory subsystem and a clock tree for balanceably sending a test signal source, the timing measurement circuit comprises:
- a plurality of TMUs, wherein each of the TMUs is coupled to a corresponding one of a plurality of pins of the memory subsystem for measuring memory parameters of the memory subsystem, each TMU comprising:
- a switch, having a control end for receiving an external switch control signal, a first end for receiving the test signal source sent by the clock tree, a second end for receiving an external data, a third end, and a fourth end;
- a plurality of series-connected delay circuits, wherein an input end of a first stage delay circuit of the delay circuits is coupled to the fourth end of the switch, a last stage of the delay circuits outputs a ring oscillator output signal, and the ring oscillator output signal indicates a resolution of the timing measurement circuit;
- and
- a multiplexer, having a control end for receiving an external delay control signal, a plurality of input ends respectively coupled to a plurality of output ends of the delay circuits, and an output end coupled to the corresponding pin of the memory subsystem;
- wherein the external switch control signal controls the operation mode of the TMU, and the external delay control signal controls a time difference between the test signal source and the output signal of the multiplexer.
A testing method of a memory, comprising:
- balanceably sending a test signal;
- respectively delaying the test signal to respectively generate a plurality of delayed test signals for being sent to a plurality of pins of the memory;
- and
- checking whether an output data output by the memory is correct and adjusting the timing of the delayed test signals input to the pins of the memory, so as to measure an AC timing parameter of the memory.
Dependencies are inferred from the claim text.