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US 2009/0158103 A1Published application
Test apparatus and test method
AssigneeAdvantest Corporation
InventorsToshiaki Awaji, Takashi Sekino, Takayuki Nakamura
Life of this patent
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AssigneeAdvantest Corporation
InventorsToshiaki Awaji, Takashi Sekino, Takayuki Nakamura
Estimating the term…
The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase difference between the first and second delay clock signals to a desired phase difference; a deciding section that decides the quality of the data signal from the DUT based on a result obtained by acquiring the delay data signal when the second delay clock signal is changed.
-7. (canceled)
A test apparatus for testing a device under test, the device under test outputting a data signal and a clock signal defining a timing of acquiring the data signal, the test apparatus comprising:
A test method for testing a device under test, the device under test outputting a data signal and a clock signal defining a timing of acquiring the data signal, the test method comprising:
Dependencies are inferred from the claim text.