US 2009/0158087 A1Published application

Semiconductor integrated circuit with memory repair circuit

AssigneeRenesas Technology Corp.

InventorsHideshi Maeno, Wataru Uchida, Michinobu Nakao, Tatsuya Saito, Mitsuo Serizawa

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Abstract

A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

Claims30

Dependent claims

A semiconductor integrated circuit comprising:

a plurality of memory circuits each including a redundancy memory and each having a data input/output function of at least one bit;
a plurality of comparators provided corresponding to the plural memory circuits and operable to obtain a comparison result by comparing data output of the plural memory circuits with an expectation value;
a plurality of result latch units provided corresponding to the plural comparators and operable to store a comparison result of the plural comparators as a plurality of latch data groups, the plural result latch units being mutually coupled in series in the case of a shift mode so as to perform shift operation among the plural latch data groups and being able to perform serial output externally as a repair analysis scan-path signal;
a repair analysis circuit operable to sequentially take in the repair analysis scan-path signal in the case of the shift mode, and operable to obtain repair analysis information indicative of the existence or nonexistence of necessity of repair and a failure location requiring repair with respect to the plural memory circuits, based on the repair analysis scan-path signal;
and
a repair decoder operable to perform repair control to replace the failure location with the redundancy memory to a memory circuit requiring repair among the plural memory circuits, based on repair control information related to the repair analysis information.

3 more elements

A semiconductor integrated circuit comprising:

a memory circuit including a redundancy memory and having a data input/output function of predetermined number of bits;
and
a data input/output controller operable to control data input/output of the predetermined number of bits in the memory circuit,
wherein the data input/output controller includes:
a one-bit input/output controller of predetermined number of bits, provided corresponding to the data input/output of the predetermined number of bits and having a comparison circuit of predetermined number of bits which obtains sequentially a comparison result of the predetermined number of bits by comparing each data output of the predetermined number of bits of the memory circuit with an expectation value;
an encoding circuit operable to sequentially generate encoded data of a smaller number of compressed bits than the predetermined number of bits, based on the comparison result of the predetermined number of bits;
and
a capture circuit having a latch circuit of the number of compressed bits, the capture circuit being operable to sequentially receive the encoded data of the number of compressed bits and operable to latch, to the latch circuit of the number of compressed bits, one piece of encoded data having the number of compressed bits and satisfying a predetermined condition,
wherein the encoded data of the number of compressed bits is capable of indicating at least first failure information on non-existence of a failure bit and second failure information on existence of one-bit failure and the bit location, with respect to the data input/output of the predetermined number of bits.

6 more elements

Dependencies are inferred from the claim text.