US 2009/0158076 A1 · TECHNIQUE TO IMPLEMENT CLOCK-GATING

Abstract

A system and method for providing clock gating while reducing area and power on an integrated circuit (IC) chip. An array of registers or memory cells may have a single clock gating circuit, rather than multiple circuits such as one clock gating circuit for each bit of storage. The single clock gating circuit may be larger in size than each of the multiple clock gating circuits, but the single clock gating circuit may still have less capacitive loading. A reduction in overall allocated area allows floorplanning to offer less congested signal routing. Clock generation circuitry may be configured to provide a clock signal from a last ungated stage to clock enabling circuitry. A power reduction control unit may be configured to determine when the last ungated stage clock waveform is enabled/disabled within the clock gating circuitry.

Claims20

Dependent claims

A system comprising:

a plurality of arrays, wherein each array comprises a plurality of storage element cells and clock enabling circuitry;
clock generation circuitry comprising a plurality of ungated stages, wherein the clock generation circuitry is configured to provide a clock signal from a last ungated stage to clock enabling circuitry;
and
a power reduction control unit configured to determine when the last ungated stage is enabled;
wherein the clock enabling circuitry is configured to:
receive the clock signal from the last ungated stage;
receive a common enable signal corresponding to the storage element cells;
and
provide a clock signal to the storage element cells, in response to detecting the last ungated stage clock signal is asserted and the common enable signal is asserted.

6 more elements

Dependencies are inferred from the claim text.

Technique to implement clock-gating

Life of this patent

Technique to implement clock-gating

Life of this patent

Abstract

Claims20