Reducing core wake-up latency in a computer system

An apparatus comprising:

• a first, a second, and a third core, and
• a power control unit coupled to the first, second, and the third core,
• wherein the power control unit is to detect a first, second, and a third interrupt directed at the first, second, and a third core,
• wherein the power control unit is to check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete, and
• wherein the power control unit is to wake-up the second and the third core concurrently if the second interrupt occurs within the first period.

A computing device comprising:

• a plurality of input-output devices,
• a chipset coupled to plurality of input-output devices,
• a multi-core processor coupled to the chipset, wherein the multi-core processor is to include a first, a second, and a third core and a power control unit coupled to the first, second, and the third core,
• wherein the power control unit is to detect a first, second, and a third interrupt directed at the first, second, and a third core,
• wherein the power control unit is to check whether the second interrupt occurs within a first period, wherein the first period is counted after waking-up of the first core is complete, and
• wherein the power control unit is to wake-up the second and the third core concurrently if the second interrupt occurs within the first period.