System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor

A superscalar microprocessor for executing instructions having a program order, the microprocessor comprising:

• a temporary buffer comprising a plurality of temporary buffer locations configured to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations, each group of temporary buffer locations including a number (N) of the temporary buffer locations, the number N being greater than 1;
• tag assignment logic configured to assign tags to instructions, wherein each tag identifies one of the temporary buffer locations,
• wherein the tag assignment logic is further configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the number of instructions in the first set of instructions is at least 1 and not more than the number N, and wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations;
• a plurality of functional units configured to execute instructions from at least the first set of instructions out of the program order, thereby generating result data for each of the instructions in the first set of instructions;
• a plurality of data paths configured to transfer result data from the functional units to the temporary buffer, wherein the result data for each instruction in the first set of instructions is transferred to the temporary buffer location identified by the tag assigned to that instruction;
• a register array including a plurality of array locations for storing result data for instructions that have been retired;
• a retirement control block configured to determine whether execution of all of the instructions in the first set of instructions is complete;
• and
• a superscalar instruction retirement unit configured to concurrently retire all of the instructions in the first set of instructions after execution of all of the instructions in the first set of instructions is complete, wherein retiring at least one of the instructions in the first set of instructions includes transferring the result data for the at least one instruction from the temporary buffer location identified by the tag assigned to the at least one instruction to a selected one of the array locations in the register array.