Method and Apparatus Implementing a Minimal Area Consumption Multiple Addend Floating Point Summation Function in a Vector Microprocessor
AssigneeInternational Business Machines Corporation
InventorsAdam J. Muff, Matthew R. Tubbs
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Abstract
Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises transferring more than two operands to a vector unit, each operand being transferred to a respective one of a plurality of processing lanes of the vector unit. The operands may be transferred from the vector unit to a dot product unit wherein an arithmetic operation using the more than two operands may be performed.
Claims23
A method for computing an arithmetic result of more than two operands, comprising:
- in response to receiving a multiple operand instruction, transferring more than two operands from a register file to a vector unit, wherein each operand is transferred to a respective one of a plurality of processing lanes of the vector unit;
- transferring each of the more than two operands from respective processing lanes of the vector unit to a dot product unit;
- and
- computing an arithmetic result of the more than two operands in the dot product unit.
A method for computing a sum of three operands, comprising:
- in response to receiving a three addend instruction, transferring three operands from a register file to a vector unit, wherein each of the three operands are transferred to a respective one of a plurality of processing lanes of the vector unit;
- transferring each of the three operands from respective processing lanes of the vector unit to a dot product unit;
- and
- computing a sum of the three operands in the dot product unit.
A system comprising a plurality of processors communicably coupled with one another, wherein each processor comprises:
- a register file comprising a plurality of registers, each register comprising a plurality of operands;
- a vector unit comprising a plurality of vector processing lanes and configured to receive more than two operands, each operand being received in a respective one of a plurality of processing lanes of the vector unit, and transfer the more than two operands to a dot product unit;
- and
- the dot product unit configured to receive each of the more than two operands from respective processing lanes of the vector unit and compute an arithmetic result of the more than two operands.
Dependencies are inferred from the claim text.