Scaleable array of micro-engines for waveform processing
AssigneeITT Manufacturing Enterprises, Inc.
InventorPatrick A. McCabe
Life of this patent
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Abstract
A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.
Claims21
A system for implementing waveform processing in a software defined radio (SDR) comprising
- a scaleable array processor including a plurality of micro-engines interconnected by a two dimensional topology,
- each micro-engine including multiple FIFOs for interconnecting to each other in the two dimensional topology,
- one micro-engine communicating with another adjacent micro-engine by way of the respective FIFOs, and
- the micro-engines dedicated to predetermined algorithms.
An array processing system comprising
- a plurality of processing engines interconnected as an array processor,
- each processing engine including multiple FIFOs,
- at least one FIFO of the multiple FIFOs of each processing engine providing an interconnection to at least another FIFO of the multiple FIFOs of another processing engine,
- each processing engine having an independent local memory,
- each processing engine having an independent instruction memory coupled to an independent microprocessor for executing multiple independent instructions, and
- the multiple FIFOs of each processing engine configured to transmit parallel bits of data received from other processing engines to the respective independent microprocessor,
- wherein the transmitted parallel bits of data are operated on by the respective independent microprocessor, executing an independent instruction arriving from the respective independent instruction memory.
An array processing system comprising
- a plurality of processing engines interconnected as an array processor,
- each processing engine including multiple FIFOs,
- at least one FIFO of the multiple FIFOs of each processing engine providing an interconnection to at least another FIFO of the multiple FIFOs of another processing engine,
- each processing engine having an independent local memory,
- each processing engine having an independent instruction memory coupled to an independent microprocessor for executing multiple independent instructions,
- each processing engine including a plurality of registers for executing the multiple independent instructions,
- the plurality of registers from each processing engine coupled to a multiplexer network, and
- a debug port coupled between the multiplexer network and a host processor,
- wherein the host processor is configured to query each of the plurality of registers and receive data stored in the queried register by way of the multiplexer network for debug examination.
An array processing system comprising
- a plurality of processing engines interconnected as an array processor,
- each processing engine including multiple FIFOs,
- at least one FIFO of the multiple FIFOs of each processing engine providing an interconnection to at least another FIFO of the multiple FIFOs of another processing engine,
- each processing engine having an independent local memory,
- each processing engine having an independent instruction memory coupled to an independent microprocessor for executing multiple independent instructions, and
- the multiple FIFOs of each processing engine transmitting parallel bits of data received from other processing engines to the respective independent microprocessor,
- wherein the parallel bits of data are operated on by the respective independent microprocessor executing an independent instruction arriving from the respective independent instruction memory,
- each processing engine includes an active mode and an inactive mode, and
- a clock is configured to sequence each processing engine during execution of the multiple independent instructions,
- wherein the active mode includes executing the multiple independent instructions and the inactive mode includes not executing the multiple independent instructions,
- each processing engine is configured to monitor the respective multiple FIFOs for presence of the parallel bits of data, and
- when the respective multiple FIFOs of a processing engine are empty, the clock is gated OFF to place the processing engine in the inactive mode, and
- when the respective multiple FIFOs of the processing engine include data, the clock is gated ON to place the processing engine in the active mode.
Dependencies are inferred from the claim text.