Mechanism for enabling full data bus utilization without increasing data granularity
AssigneeRambus Inc.
InventorBilly GARRETT, JR.
Life of this patent
Estimating the term…
Abstract
A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.
Claims20
A method for controlling a memory, comprising:
- issuing a first row access request to the memory during a first clock cycle of a reference clock;
- issuing a column access request to the memory during the first clock cycle;
- and
- issuing a second row access request to the memory during a second clock cycle of the reference clock, wherein the second clock cycle immediately follows the first clock cycle.
The method of claim 8 wherein the column access request comprises a column address that specifies a column of data within the one of the plurality of rows of storage cells.
A memory controller comprising:
- a first interface to receive memory access requests from an external component;
- and
- request circuitry, responsive to the memory access requests from the external component, to issue (i) a first row access request to a memory during a first clock cycle of a reference clock, (ii) a column access request to the memory during the first clock cycle, and (iii) a second row access request to the memory during a second clock cycle of the reference clock, wherein the second clock cycle immediately follows the first clock cycle.
A memory controller comprising:
- means for issuing a first row access request to a memory during a first clock cycle of a reference clock;
- means for issuing a column access request to the memory during the first clock cycle;
- and
- means for issuing a second row access request to the memory during a second clock cycle of the reference clock, wherein the second clock cycle immediately follows the first clock cycle.
Dependencies are inferred from the claim text.