Memory controller
AssigneeSamsung Electronics Co., Ltd.
InventorsKwan-ho Kim, Jong-in Kim, Young-wook Jang, Dae-woong Kim, Bong-chun Kang
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Abstract
A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.
Claims20
A memory controller comprising:
- a programmable delay unit configured to receive a periodic read-enable signal and to output a delayed periodic read-enable signal having a variable delay time selected in response to an externally applied delay-control signal;
- and
- a sampling unit configured to output, in synchronization with the delayed periodic read-enable signal, data read out from a memory coupled to the memory controller,
- wherein the delay time is a first multiple of the period of a clock signal.
16 The memory controller of claim 10, wherein the number n of delay cells is predetermined according to a rated maximum value of the access time of the memory controller.
A memory controller comprising:
- a digitally programmable delay unit having a variable delay time configured to receive a periodic read-enable signal and to output a delayed periodic read-enable signal;
- a sampling unit configured to latch and output, in synchronization with the delayed periodic read-enable signal, data read out from a memory coupled to the memory controller,
- wherein the memory controller is formed on a first integrated circuit and the memory is formed on a separate second integrated circuit.
Dependencies are inferred from the claim text.