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US 2009/0157980 A1Published application
Memory controller with write data cache and read data cache
AssigneeArm Limited
InventorAlistair Crone Bruce
Life of this patent
Estimating the term…
Abstract
A memory controller 14 includes a write data cache 18, a read data cache 20 and coherency circuitry 22. The coherency circuitry 22 manages coherency of data between the write data cache 18, the read data cache 20 and data stored within a main memory 16 when servicing read requests and write requests received by the memory controller 14. Write complete signals are issued back to a write requesting circuit as soon as a write request has had its write data stored within the write data cache 18.
Claims20
A memory controller comprising:
- a write data cache having a plurality of write cache lines respectively storing write data to be written to a memory;
- a read data cache separate from said write data cache and having a plurality of read cache lines respectively storing read data read from said memory;
- and
- coherency circuitry coupled to said write data cache and said read data cache and responsive to access requests to said memory to manage coherency between said write data, said read data and data stored within said memory.
1 more element
A memory controller comprising:
- write data cache means having a plurality of write cache line means respectively for storing write data to be written to a memory;
- read data cache means separate from said write data cache means and having a plurality of read cache line means respectively for storing read data read from said memory;
- and
- means for managing coherency coupled to said write data cache means and said read data cache means and responsive to access requests to said memory to manage coherency between said write data, said read data and data stored within said memory.
1 more element
A method of controlling a memory, said method comprising the steps of:
- storing write data to be written to a memory in respective write cache lines of a write data cache;
- storing read data read from said memory in respective read data lines of a read data cache, said read data cache being separate from said write data cache;
- and
- managing coherency between said write data, said read data and data stored within said memory.
1 more element
Dependencies are inferred from the claim text.