Cache injection using speculation

A system for cache injection using speculation, comprising:

• an input/output (I/O) system comprising at least one of a system chipset and an input/output (I/O) hub, the I/O transaction including an address;
• and
• logic executed on the I/O system, the logic performing:
• creating a cache line indirection table at an input/output (I/O) hub, the cache line indirection table including fields and entries for addresses or address ranges, processor ID, and cache type and includes cache level line limit fields for cache levels CLL1 through CLLn, where CLL1 is the lowest level cache limit in a hierarchically organized cache system;
• setting cache line limits to the cache level line limit fields;
• receiving a stream of contiguous addresses A1 through An at the cache line indirection table;
• and
• for each address in the stream:
• looking up the address in the cache line indirection table;
• if the address is present in the cache line indirection table, inject the cache line corresponding to the address in the processor complex;
• if the address is not present in the cache line indirection table, search limit values from the lowest level cache to the highest level cache;
• and
• inject addresses not present in the cache line indirection table to the cache hierarchy of the processor last injected from the contiguous address stream, the processor last injected has a cached address present in the cache line indirection table, performing injection from lowest level cache to highest level, observing all limit rules.

A computer program product for cache injection using speculation, the computer program product comprising:

• a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for implementing a method, the method comprising:
• creating a cache line indirection table at an input/output (I/O) hub, the cache line indirection table including fields and entries for addresses or address ranges, processor ID, and cache type and includes cache level line limit fields for cache levels CLL1 through CLLn, where CLL1 is the lowest level cache limit in a hierarchically organized cache system;
• setting cache line limits to the cache level line limit fields;
• receiving a stream of contiguous addresses A1 through An at the cache line indirection table;
• and
• for each address in the stream:
• looking up the address in the cache line indirection table;
• if the address is present in the cache line indirection table, inject the cache line corresponding to the address in the processor complex;
• if the address is not present in the cache line indirection table, search limit values from the lowest level cache to the highest level cache;
• and
• inject addresses not present in the cache line indirection table to the cache hierarchy of the processor last injected from the contiguous address stream, the processor last injected has a cached address present in the cache line indirection table, performing injection from lowest level cache to highest level, observing all limit rules.