Cache memory unit with early write-back capability and method of early write back for cache memory unit
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung Jin CHUNG, Kil Whan LEE
Life of this patent
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Abstract
A cache memory unit includes: a cache memory; an early write-back condition checking unit for checking whether an early write-back condition has been satisfied; and an early write-back execution unit for monitoring a memory bus connecting the cache memory unit and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the external memory unit using the memory bus.
Claims32
A cache memory unit, comprising:
- a cache memory;
- an early write-back condition checking unit for checking whether an early write-back condition has been satisfied;
- and
- an early write-back execution unit for monitoring a memory bus connecting the cache memory unit and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the external memory unit using the memory bus.
A write buffer for a data processing system, comprising:
- a buffer memory;
- an early write-back condition checking unit for checking whether an early write-back condition has been satisfied;
- and
- an early write-back execution unit for monitoring a memory bus connecting the write buffer and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the buffer memory to be written back to the external memory unit using the memory bus.
A method of operating a memory device connected via a memory bus with an external memory unit, the method comprising:
- (a) determining whether an early write-back condition is satisfied;
- (b) determining whether a data block is dirty;
- (c) determining whether the memory bus is idle;
- and
- (d) when the early write-back condition is satisfied, and the data block is dirty, then writing the dirty data block back from the memory device to the external memory unit when the memory bus is idle.
A processing system, comprising:
- a processor;
- a main memory unit;
- a cache memory unit;
- and
- a memory bus connecting the cache memory unit and the main memory unit,
- wherein the cache memory unit comprises:
- a cache memory;
- an early write-back condition checking unit for checking whether an early write-back condition has been satisfied;
- and
- an early write-back execution unit for monitoring the memory bus, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the main memory unit using the memory bus.
A method of operating a processing system comprising a processor, a main memory unit, a memory device, and a memory bus connecting the memory device and the main memory unit, the method comprising:
- (a) providing data and a write address from the processor to the cache memory unit;
- (b) determining whether an early write-back condition is satisfied;
- (c) determining whether a data block corresponding to the write address is dirty;
- (d) determining whether the memory bus is idle;
- and
- (e) when the early write-back condition is satisfied, and the data block is dirty, then writing the dirty data block back from the memory device to the external memory unit when the memory bus is idle.
Dependencies are inferred from the claim text.