Semiconductor memory system and wear-leveling method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsSoo-Jeong Kim, Jun-Young Cho, Min-Soo Moon
Life of this patent
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Abstract
Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type. The semiconductor memory system is improved in performance and lifetime by managing wearing degrees over the logic block or the entries in accordance with the data type.
Claims24
A semiconductor memory system comprising:
- a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries;
- a file system that detects a type of data to be stored and allocates a logic block or an entry for storing the data in accordance with the data type;
- and
- a translation layer that levels wearing degrees over the logic blocks or the entries in accordance with the data type.
A wear-leveling method for a semiconductor memory system having a plurality of logic blocks each of which is divided into a plurality of entries, the method comprising:
- detecting a type of data to be stored and allocating the logic block or the entry for the data in accordance with the data type;
- and
- managing wearing degrees over the logic block or the entries in accordance with the data type.
Dependencies are inferred from the claim text.