Address translation between a memory controller and an external memory device

An address translation system for translating between a logical address and a physical address, the system comprising:

• a NAND flash memory device comprising a memory controller coupled to a NAND non-volatile memory array;
• an external volatile memory device that is separate from the NAND flash memory device and stores address translation information accessible by the memory controller;
• and
• a dedicated serial data bus connected between the memory controller and the external volatile memory device to enable the memory controller to access the address translation information.

A method for memory address translation comprising:

• a non-volatile memory device memory controller accessing with a logical memory address, over a dedicated serial bus, an address translation table in a volatile memory device external from the non-volatile memory device;
• the memory controller retrieving a physical memory address, corresponding to the logical memory address, from the translation table;
• and
• the memory controller performing a memory operation on a non-volatile memory array of the non-volatile memory device at least partially in response to the physical memory address.

A memory system comprising:

• a processor for controlling operation of the memory system and generating memory signals;
• and
• a non-volatile memory device coupled to the processor and operating at least partially in response to the memory signals, the memory device comprising:
• a non-volatile memory array coupled to a memory controller, the memory controller coupled to the processor through a memory controller interface;
• and
• a DRAM coupled to the memory controller over a dedicated serial bus that connects only the DRAM and the memory controller, the DRAM comprising data for translating between a logical memory address and a physical memory address.

A method for memory address translation comprising:

• a non-volatile memory device memory controller determining logical memory addresses for columns of a memory array that are defective;
• the memory controller accessing address mapping data with the logical memory addresses, over a dedicated serial bus, from a volatile memory device external from the non-volatile memory device;
• and
• the memory controller determining, from the address mapping data, physical memory addresses corresponding to the logical memory addresses.