Interrupt morphing and configuration, circuits, systems, and processes

An electronic power management system comprising:

• plural processors operable in different execution environments and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one interrupt output;
• a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs;
• a first configuration register coupled to at least one of said processors for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment is activated;
• and
• a second configuration register for associating an identification of that execution environment with the same interrupt request, at least one of said processors coupled to said second configuration register to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment is suspended, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.

An electronic debug circuit comprising

• a scan controller operable for serially providing a multi-bit scan signal at a scan output and receiving a multi-bit scan signal at a scan input;
• and
• a first configuration register coupled to said processing circuit for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment is activated;
• and
• a second configuration register for associating an identification of that execution environment with the same interrupt request;
• and
• a circuit coupled to said second configuration register to output the same interrupt request as a more urgent type of interrupt request when that execution environment is suspended, said second configuration register coupled to said scan output and to said scan input of said scan controller.

A method of operating an electronic circuit having an interrupt controller responsive to a plurality of interrupt initiator lines and further having at least one interruptible processor having at least first and second interrupt input lines for vectoring to different interrupt addresses and the processor operable in different execution environments, the method comprising:

• using a first configuration register coupled to said processing circuit to associate each interrupt initiator line to an execution environment;
• establishing a first identification of each interrupt initiator line associated to a given execution environment as an ordinary interrupt request IRQ when the given execution environment is activated and routing such IRQ to the first interrupt input line to the processor;
• and
• alternately establishing a second identification of each interrupt initiator line associated to the given execution environment as a fast interrupt request FIQ when the given execution environment is suspended and routing such FIQ to the second interrupt input line to the processor.

A telecommunications apparatus comprising:

• a wireless modem;
• a processing system coupled to said wireless modem and including plural processor cores operable in various execution environments and a first configuration register coupled to said processing circuit for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment is activated and a second configuration register for associating an identification of that execution environment with the same interrupt request, said processing system coupled to said second configuration register to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment is suspended;
• and
• a user interface coupled to said processing system.

An electronic circuit for routing interrupt signals to an IRQ output and FIQ output to interrupt a processor that is operable in various execution environments (EEs), the electronic circuit comprising:

• a plurality of interrupt lines for carrying interrupt signals;
• a suspend control circuit operable to generate a multi-bit routing representation depending on at least one of the EEs being active or suspended;
• and a
• a routing circuit coupled to said suspend control circuit and operable for selectively coupling each of said plurality of interrupt lines to one or the other of the IRQ output and FIQ output in response to the routing representation.