Efficient interrupt message definition
AssigneeMicrosoft Corporation
InventorsBruce Worthington, Vinod Mamtani, Brian Railing
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AssigneeMicrosoft Corporation
InventorsBruce Worthington, Vinod Mamtani, Brian Railing
Estimating the term…
An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group.
A method of operating a computer, the computer comprising a plurality of processors and a plurality of devices adapted to issue interrupts, each interrupt to be serviced by a processor of the plurality of processors, the processors being configured in a plurality of groups based on proximity, and the method establishing messages for each of the plurality of devices, each message for use in interrupting a processor of the plurality of processors, the method comprising:
A computer comprising:
A method of operating a computer, the computer comprising a plurality of devices adapted to issue interrupts, each interrupt to be serviced by a processor of the plurality of processors, the processors being configured in a plurality of groups based on proximity, and the method establishing a plurality of messages for each of the plurality of devices to use in interrupting a processor of the plurality of processors, the method comprising:
Dependencies are inferred from the claim text.