Communication bus power state management
AssigneeIntel Corporation
InventorsShaun Conrad, Robert Safranek, Selim Bilgin
Life of this patent
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Abstract
Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.
Claims21
A computer based method to manage a power state of a communication bus in an electronic device, comprising:
- transmitting a first power state change request from a master node on the communication bus to a first slave node on the communication bus;
- receiving the first power state change request in the first slave node;
- determining whether the first slave node can accept the power change request;
- and
- changing the status of the first slave node to a master node when the first slave node cannot accept the first power state change request.
An electronic apparatus comprising:
- a bus including a master node and at least a first slave node;
- a processor;
- a memory module comprising logic instructions stored on a computer readable medium which, when executed on the processor, configure the processor to:
- transmit a first power state change request from the master node to the first slave node;
- receive the first power state change request in the first slave node;
- determine whether the first slave node can accept the power change request;
- and
- change the status of the first slave node to a master node when the first slave node cannot accept the first power state change request.
A system comprising:
- a memory module;
- a first integrated circuit device;
- a second integrated circuit device;
- a bus to provide communication between the first integrated circuit device and the second integrated circuit device, the bus including a master node and at least a first slave node;
- a memory module comprising logic instructions stored on a computer readable medium which, when executed on a processor, configure the processor to:
- transmit a first power state change request from the master node to the first slave node;
- receive the first power state change request in the first slave node;
- determine whether the first slave node can accept the power change request;
- and
- change the status of the first slave node to a master node when the first slave node cannot accept the first power state change request.
A computer based method to manage a power state of a communication bus in an electronic device, comprising:
- designating a first node as a master node on a point-to-point bus;
- originating a first power state change request from the master node;
- and
- reassigning the master node to a second node on the point-to-point bus when the first power state change request is denied.
A bus controller, comprising:
- a memory module comprising logic instructions stored on a computer readable medium which, when executed on a processor, configure the controller to:
- designate a master node on a point-to-point bus;
- originate a first power state change request from the master node;
- and
- reassign the master node when the first power state change request is denied.
Dependencies are inferred from the claim text.