Methods of Forming Trench Isolation and Methods of Forming Floating Gate Transistors

A method of forming trench isolation, comprising:

• forming mask lines over a semiconductor substrate;
• forming sidewall spacers on sidewalls of the mask lines;
• etching first trench lines into semiconductive material of the semiconductor substrate between the sidewall spacers using the mask lines and sidewall spacers as a first etching mask;
• forming first isolation material within the first trench lines within the semiconductive material;
• after forming the first isolation material within the first trench lines, etching the mask lines from the substrate selectively relative to the sidewall spacers;
• after etching the mask lines from the substrate, etching second trench lines into semiconductive material of the semiconductor substrate using the sidewall spacers and the first isolation material within the first trench lines as a second etching mask;
• and
• forming second isolation material within the second trench lines within the semiconductive material.

A method of forming trench isolation, comprising:

• etching first trench lines into semiconductive material of a semiconductor substrate, the first trench lines having respective maximum open widths within the semiconductive material of no greater than 35 nanometers, the semiconductive material between adjacent first trench lines having respective minimum widths which are at least twice that of said respective maximum open widths of the first trench lines;
• filling the first trench lines within the semiconductive material;
• after filling the first trench lines, etching second trench lines into semiconductive material of the semiconductor substrate between the first trench lines such that the first and second trench lines alternate, the second trench lines having respective maximum open widths within the semiconductive material which are no greater than 35 nanometers, the semiconductive material between adjacent first and second trench lines having respective minimum widths which are no greater than 35 nanometers;
• and
• filling the second trench lines within the semiconductive material.

A method of forming trench isolation, comprising:

• forming mask lines over a semiconductor substrate;
• forming sidewall spacers on sidewalls of the mask lines;
• etching first trench lines into semiconductive material of the semiconductor substrate between the sidewall spacers using the mask lines and sidewall spacers as a first etching mask;
• depositing first isolation material to within and overfilling the first trench lines within the semiconductive material to be received between adjacent of the sidewall spacers and to be received elevationally over the mask lines and sidewall spacers;
• removing the first isolation material effective to expose the mask lines;
• after the removing, etching the mask lines from the substrate selectively relative to the sidewall spacers;
• after etching the mask lines from the substrate, etching second trench lines into semiconductive material of the semiconductor substrate using the sidewall spacers and the first isolation material within the first trench lines as a second etching mask;
• depositing second isolation material to within and overfilling the second trench lines within the semiconductive material;
• and
• removing the sidewall spacers from the substrate after etching the mask lines from the substrate.

A method of forming floating gate transistors, comprising:

• forming floating gate material over first gate dielectric material over semiconductive material of a semiconductor substrate;
• forming mask lines over the floating gate material;
• forming sidewall spacers on sidewalls of the mask lines;
• etching first trench lines into the floating gate material, the first gate dielectric material, and the semiconductive material of the semiconductor substrate between the sidewall spacers using the mask lines and sidewall spacers as a first etching mask;
• forming first isolation material within the first trench lines within the semiconductive material;
• after forming the first isolation material within the first trench lines, etching the mask lines from the substrate selectively relative to the sidewall spacers;
• after etching the mask lines from the substrate, etching second trench lines into the floating gate material, the gate first dielectric material, and the semiconductive material of the semiconductor substrate using the sidewall spacers and the first isolation material within the first trench lines as a second etching mask;
• forming second isolation material within the second trench lines within the semiconductive material;
• and
• after forming the second isolation material with the second trench lines, forming second gate dielectric material over the floating gate material and forming control gate material over the second gate dielectric material.