Enhanced multi-bit non-volatile memory device with resonant tunnel barrier
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
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Abstract
A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control gate is formed over the charge blocking layer. Another embodiment forms a floating gate over the tunnel barrier that is comprised of two oxide layers with an amorphous layer of silicon and/or germanium between the oxide layers.
Claims20
A method for fabricating a non-volatile memory cell in a substrate, the method comprising:
- doping a pair of source/drain regions in the substrate;
- forming a first layer of a resonant tunnel barrier over the substrate, the first layer comprising HfSiON;
- forming a second layer of one of amorphous silicon or amorphous germanium over the first layer;
- forming a third layer of the resonant tunnel barrier over the amorphous layer, the third layer comprising HfSiON;
- forming a charge trapping layer over the resonant tunnel barrier;
- forming a charge blocking layer over the charge trapping layer;
- and
- forming a gate over the charge blocking layer.
A method for fabricating a non-volatile memory cell in a substrate, the method comprising:
- doping a pair of source/drain regions in the substrate;
- forming a first layer of a resonant tunnel barrier over the substrate, the first layer comprising LaAlO3;
- forming a second layer of one of amorphous silicon or amorphous germanium over the first layer;
- forming a third layer of the resonant tunnel barrier over the amorphous layer, the third layer comprising LaAlO3;
- forming a charge trapping layer over the resonant tunnel barrier;
- forming a high-k charge blocking layer over the charge trapping layer;
- and
- forming a control gate over the charge blocking layer.
A method for fabricating a non-volatile memory cell in a substrate, the method comprising:
- forming a pair of source/drain regions in the substrate;
- forming a resonant tunnel barrier on the substrate, the resonant tunnel barrier comprising:
- a first layer composed of one of HfiON or LaAlO3;
- a second layer of one of amorphous silicon or amorphous germanium on the first layer;
- a third layer on the second layer, the third layer composed of the same material as the first layer;
- forming a charge trapping layer on the third layer of the resonant tunnel barrier;
- forming a charge blocking layer on the charge trapping layer;
- and
- forming a control gate on the charge blocking layer.
Dependencies are inferred from the claim text.