Methods for fabricating an electronic device
AssigneeIndustrial Technology Research Institute
InventorsKuo-Jui Chang, Meei-Yu Hsu, Feng-Yu Yang
Life of this patent
Estimating the term…
Abstract
A method for fabricating an electronic device is provided. The method for fabricating the electrical device comprises providing a substrate. A patterned first self-assembled monolayer (SAM) and an adjacent patterned second SAM are formed on the substrate, wherein the patterned first SAM has a higher affinity then that of the patterned second SAM. A conductive, semiconductor or insulating material is dissolved or suspended in a solvent to form a solution. The solution is coated on the substrate. The solvent in the solution is removed to selectively form a patterned conductive, semiconductor or insulating layer on the patterned first SAM.
Claims20
A method for fabricating an electronic device, comprising:
- providing a substrate;
- forming a patterned first self-assembled monolayer and an adjacent patterned second self-assembled monolayer on the substrate, wherein the patterned first self-assembled monolayer has a higher affinity then that of the patterned second self-assembled monolayer;
- coating a solution on the substrate, wherein the solution is formed by dissolving or suspending a conductive, semiconductor or insulating material in a solvent;
- removing the solvent in the solution to selectively form a patterned conductive, semiconductor or insulating layer on the patterned first self-assembled monolayer;
A method for fabricating an electronic device, comprising:
- providing a substrate having a channel region and a pair of source/drain regions, wherein the pair of the source/drain regions is adjacent to two sides of the channel region, respectively;
- forming a dielectric layer on the substrate;
- forming a pair of source/drain layers on the dielectric layer in the source/drain regions;
- forming a patterned first self-assembled monolayer on the dielectric layer in the channel region and a portion of the source/drain layers adjacent to two sides of the channel region, and forming a patterned second self-assembled monolayer on the remaining source/drain layers, wherein the patterned first self-assembled monolayer has a higher affinity then that of the patterned second self-assembled monolayer;
- and
- selectively forming a semiconductor layer on the patterned first self-assembled monolayer.
Dependencies are inferred from the claim text.