High speed hybrid structure counter having synchronous timing and asynchronous counter cells
AssigneeIntegrated Device Technology, Inc.
InventorsZhuyan Shao, Juan Qiao
Life of this patent
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Abstract
A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.
Claims19
A multi-bit counter, comprising:
- a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals;
- at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells;
- a reload signal being input into the asynchronous base counter cells;
- a clock signal being input into the asynchronous base counter cells;
- and
- an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.
A phase-locked loop feedback programmable divider, comprising:
- a phase frequency detector;
- a charge pump and loop filter;
- a voltage-controlled oscillator;
- a predivider;
- and
- a programmable divider, wherein:
- the programmable divider comprises a multi-bit counter having synchronous timing, the counter including a plurality of asynchronous base counter cells coupled in series.
Dependencies are inferred from the claim text.