System and Method for Filter Response Switching

A method for efficiently switching digital filter coefficients, the method comprising:

• accepting an input signal;
• in a first timeslice, digitally filtering the input signal using base coefficients multiplied by stored filter output and input values from previous timeslices;
• supplying a first steady state filter output value;
• in response to changes in the input signal, digitally filtering the input signal in a predetermined number of intermediate period timeslices using transient coefficients multiplied by stored filter output and input values from previous timeslices;
• maintaining the first filter output value within a predetermined range;
• in a second timeslice, digitally filtering the input signal using base coefficients multiplied by stored filter output and input values from previous timeslices;
• and,
• supplying a second steady state filter output value.

A phase-locked loop (PLL) system for efficiently switching a loop bandwidth while minimizing control signal transients, the system comprising:

• a frequency generator having an input to accept a control signal and an output to supply a PLL signal;
• a frequency/phase detector having an input to accept the PLL signal, an input to accept a monitored signal, and an output to supply a detection signal;
• a digital filter having a memory, an input to accept the detection signal in a first timeslice, and an output to supply the control signal enabling a PLL first bandwidth, responsive to multiplying base coefficients by control and detection signal values stored in the memory from previous timeslices;
• wherein the filter multiplies transient coefficients by control and detection signal values stored in the memory from previous timeslices in a predetermined number of first intermediate period timeslices, in response to changes in the detection signal, and maintains the control signal within a predetermined range;
• and,
• wherein the filter supplies the control signal in a second timeslice, enabling a PLL a second bandwidth responsive to multiplying base coefficients by control and detection signal values stored in the memory from previous timeslices.

A digital filter for switching applications, the filter comprising:

• an input to accept a detection signal;
• an output to supply a control signal;
• a memory with an interface for storing and accessing control and detection signal values;
• a switch module to multiple base coefficients by stored control and detection signal values from previous timeslices and to calculate a first steady control signal value in a first timeslice;
• wherein the switch module multiplies transient coefficients by stored control and detection signal values in a predetermined number of intermediate period timeslices, to calculate the control signal value within a predetermined range;
• and,
• wherein the switch module multiplies base coefficients by stored control and detection signal values in a second timeslice to calculate a second steady control signal value.