High-speed serial data signal receiver circuitry

Multiplexer circuitry for converting successive blocks of plural parallel data bits to a serial data output signal comprising:

• first multiplexer circuitry for converting each of the successive blocks to a succession of first intermediate blocks, each of which includes a first subplurality of the bits from the block currently being processed;
• second multiplexer circuitry for converting each of the successive first intermediate blocks into a succession of second intermediate blocks, each of which includes a second subplurality of the bits from the first intermediate block currently being processed;
• and
• third multiplexer circuitry for converting each of the successive second intermediate blocks into a succession of individual bits.

Demultiplexer circuitry for converting a serial data input signal to successive blocks of plural parallel data bits comprising:

• first demultiplexer circuitry for converting successive pairs of bits in the serial data input signal to successive parallel-form bit pairs;
• second demultiplexer circuitry for converting successive groups of the parallel-form bit pairs to successive intermediate blocks of parallel data bits, each of the intermediate blocks including a plural number of the parallel-form bit pairs;
• and
• third demultiplexer circuitry for converting successive groups of the intermediate blocks to successive final groups of parallel data bits, each of the final groups including a multiple number of the intermediate blocks.

A method of converting successive blocks of plural parallel data bits to a serial data output signal comprising:

• converting each of the successive blocks to a succession of first intermediate blocks of parallel data bits, each of which first intermediate blocks includes a first subplurality of the bits from the block currently being processed;
• further converting each of the successive first intermediate blocks into a succession of second intermediate blocks of parallel data bits, each of which second intermediate blocks includes a second subplurality of the bits from the first intermediate block currently being processed;
• and
• still further converting each of the successive second intermediate blocks into a succession of the individual bits.

A method of converting a serial data input signal to successive blocks of plural parallel data bits comprising:

• converting successive pairs of bits in the serial data input signal to successive parallel-form bit pairs;
• further converting successive groups of the parallel-form bit pairs to successive intermediate blocks of parallel data bits, each of the intermediate blocks including a plural number of the parallel-form bit pairs;
• and
• still further converting successive groups of the intermediate blocks to successive final groups of parallel data bits, each of the final groups including a multiple number of the intermediate blocks.