Memory device with self-refresh operations

A memory circuit for dynamic semiconductor memories having self-refresh capability, comprising:

• an internal self-refresh circuit configured for refreshing the memory cells within the blocks of a dynamic semiconductor memory and controlling bit line equalization (BLEQ), sense amplifier enable (SAPN), isolator control signals (ISO), pre-decoded row address (PXID) and word enable (WE);
• and
• an address decoder in said internal self-refresh circuitry which is configured for decoding memory addresses in response to the inputs of address, command, row activation selection (RAS), self-refresh, and refresh counter;
• wherein said self-refresh circuit is configured for controlling the generation of one or more of the signals selected from ISO, PXID, and WE, in response to signals from the address decoder in addition to signals from said self-refresh and said refresh counter;
• and
• wherein said ISO, PXID, and/or WE signals are selectively output during self-refresh mode operations with different timing and sequencing than when the memory circuit is in a normal operating mode.

A memory circuit for dynamic memories having self-refresh capability, comprising:

• address and command buffers configured for receiving address and command information for controlling memory operations;
• a row activation selection (RAS) circuit coupled to said command buffer;
• a self-refresh circuit coupled to said command buffer;
• at least one refresh counter coupled to said self-refresh circuit;
• an address decoder configured for receiving the output from said address buffer, RAS circuit, self-refresh circuit and refresh counter;
• a block selection circuit coupled to said address decoder and configured for driving bit line equalization (BLEQ) circuits and sense amplifier enable (SAPN) circuits;
• and
• a circuit for generating isolator control signals (ISO), pre-decoded row address drivers (PXID) and plural word enable (WE) lines selected from one or more of the following:
• (i) a block iso-selection circuit configured for driving an ISO generation circuit adapted for generating isolator control signals, said block iso-selection circuit configured with separate sequencing and/or timing, than said block selection circuit, in response to self-refresh mode operations of the memory circuit, wherein said block iso-selection circuit can selectively output fewer ISO signal transitions during self-refresh mode operations of the memory circuit than when in normal operating modes;
• (ii) a pre-decoded row address driver (PXID) circuit coupled to said self-refresh control circuit and to at least one counter of said refresh counter in addition to being coupled to said address decoder, said PXID circuit configured with separate sequencing and/or timing than if coupled only to said address decoder, wherein said PXID circuit can selectively output fewer PXID signal transitions during self-refresh mode operations of the memory circuit than when in normal operating modes;
• (iii) a word enable (WE) circuit coupled to said self-refresh control circuit and to at least one counter of said refresh counter in addition to being coupled to said address decoder, said WE circuit configured with separate sequencing and/or timing than if it were only coupled to said address decoder, wherein said WE circuit can selectively output fewer WE signal transitions during self-refresh mode operations of the memory circuit than when in normal operating modes.

A method of reducing power consumption within a semiconductor memory circuit configured for self-refresh operation, comprising:

• decoding memory addresses to generate an address decoder signal in response to the receipt of address, command, row activation selection (RAS), self-refresh, and refresh counter inputs;
• generating bit line equalization (BLEQ), sense amplifier enable (SAPN), isolator control signals (ISO), pre-decoded row address (PXID) and word enable (WE) in response to said decoding of memory addresses;
• and
• controlling said ISO, or said PXID, or said WE, or a combination of said ISO, PXID, and WE, differently when in self-refresh mode than when in normal modes by receiving self-refresh and refresh counter signals within circuitry which is separate from the address decoder signal;
• wherein power consumption is reduced in response to generation of said ISO, PXID, and/or WE signals with different timing and sequencing than when the memory circuit is in a normal operating mode.