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AssigneeQUALCOMM Incorporated
InventorsMohamed R. Abu-Rahma, Ritu Chaba, Nan Chen, Sei Seung Yoon
Estimating the term…
A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.
A memory device comprising:
A method of operating a memory device having a bit line including a first section and a second section comprising:
A memory device comprising:
A method of operating a memory device having a bit line including a first section and a second section comprising the steps of:
A memory design structure tangibly embodied on a computer readable medium, comprising:
Dependencies are inferred from the claim text.