Dll circuit, imaging device, and memory device

A DLL circuit comprising:

• a variable delay circuit for successively delaying an input clock to generate a plurality of delayed clocks having different phases;
• a phase comparison circuit for receiving a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, and comparing the phases of the first and second reference clocks;
• an excessive delay state detection circuit for detecting an excessive delay state in which a difference in delay time between the first and second reference clocks is greater than one cycle;
• and
• a delay control circuit for controlling, during a time interval in which the excessive delay state detection circuit does not detect the excessive delay state, a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit, and gradually reducing the delay time in the variable delay circuit irrespective of the comparison result obtained by the phase comparison circuit during a time interval in which the excessive delay state detection circuit detects the excessive delay state.