Swapped-Body RAM Architecture
AssigneeDSM Solutions, Inc.
InventorEric H. Voelkel
Life of this patent
Estimating the term…
Abstract
A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage.
Claims24
A memory cell, comprising:
- first and second access transistors, wherein the first access transistor is connected to a word line and connected between a first bit line and a first data node, and wherein the second access transistor is connected to the word line and connected between a second bit line and a second data node;
- first and second pull-up transistors, wherein the first pull-up transistor is connected to a first power supply point and to the first data node, and wherein the second pull-up transistor is connected to the first power supply point and the second data node;
- first and second pull-down transistors, wherein the first pull-down transistor is connected to a second power supply point and to the first data node, and wherein the second pull-down transistor is connected to the second power supply point and to the second data node;
- wherein the memory cell can perform a read operation, a write operation, or reside in an idle state;
- and
- wherein during a read operation the first and second pull-up transistors, the first and second pull-down transistors, and the first and second access transistors receive a forward bias voltage.
A memory cell, comprising:
- first and second access transistors, wherein the first access transistor is connected to a word line and connected between a first bit line and a first data node, and wherein the second access transistor is connected to the word line and connected between a second bit line and a second data node;
- first and second pull-up transistors, wherein the first pull-up transistor is connected to a first power supply point and to the first data node, and wherein the second pull-up transistor is connected to the first power supply point and the second data node;
- first and second pull-down transistors, wherein the first pull-down transistor is connected to a second power supply point and to the first data node, and wherein the second pull-down transistor is connected to the second power supply point and to the second data node;
- wherein the memory cell can perform a read operation, a write operation, or reside in an idle state;
- and
- wherein during a write operation the first and second pull-up transistors receive a zero or reverse bias voltage, and wherein the first and second pull-down transistors and the first and second access transistors receive a forward bias voltage.
A method for biasing an SRAM cell, comprising:
- during a read operation, forward biasing an N-well that contains a first and second pull-up transistor to zero volts, and forward biasing a P-well, residing within the N-well, that contains a first and second pull-down transistor and a first and second access transistor to a power supply voltage;
- during a write operation, zero or reverse biasing the N-well that contains the first and second pull-up transistors to the power supply voltage, and forward biasing the P-well that contains the first and second pull-down transistors and the first and second access transistors to the power supply voltage;
- and
- during an idle state, zero biasing the N-well that contains the first and second pull-up transistors to the power supply voltage, and zero biasing the P-well that contains the first and second pull-down transistors and the first and second access transistors to zero volts.
Dependencies are inferred from the claim text.