Integrated Circuit Memory Devices Including Delayed Clock Inputs for Input/Output Buffers and Related Systems and Methods

A method of operating a memory system including an integrated circuit memory device with a memory cell array having a plurality of memory cells and a plurality of data input/output buffers coupled between respective data input/output pads and the memory cell array, and including a memory controller coupled to the plurality of input/output buffers, the method comprising:

• generating a clock signal;
• providing a delay so that the clock signal is delayed by different amounts at clock inputs of at least first and second ones of the data input/output buffers;
• communicating data between the plurality of data input/output buffers and the memory cell array responsive to the clock signal received at the respective clock inputs of the input/output buffers;
• and
• performing data training between the memory controller and the plurality of data input/output buffers.

An integrated circuit memory device comprising:

• a memory cell array including a plurality of memory cells;
• a clock generator configured to generate a clock signal;
• a plurality of data input/output buffers coupled between respective data input/output pads and the memory cell array, wherein each of the data input/output buffers is configured to communicate data with the memory cell array responsive to the clock signal wherein the clock signal is applied to a clock input of each of the input/output buffers;
• and
• a delay circuit coupled between the clock generator and a first one of the data input/output buffers so that the clock signal is delayed by different amounts at clock inputs of the first data input/output buffer and a second one of the data input/output buffers.

An integrated circuit memory device comprising:

• a memory cell array including a plurality of memory cells;
• a clock generator configured to generate a clock signal;
• a plurality of data input/output buffers coupled between respective data input/output pads and the memory cell array, wherein each of the data input/output buffers is configured to communicate data between a memory controller and the memory cell array responsive to the clock signal wherein the clock signal is applied to a clock input of each of the input buffers;
• a plurality of variable delay circuits wherein each variable delay circuit is coupled between the clock signal generator and a respective one of the data input/output buffers wherein each of the variable delay circuits is configured to provide one of a plurality of different time delays for the clock signal;
• and
• a delay controller coupled to each of the variable delay circuits wherein the delay controller is configured to select a respective delay to be provided by each of the variable delay circuits.

A memory system comprising:

• an integrated circuit memory device including:
• a memory cell array having a plurality of memory cells,
• a clock generator configured to generate a clock signal,
• a plurality of data input/output buffers coupled between respective data input/output pads and the memory cell array, wherein each of the data input/output buffers is configured to communicate data between a memory controller and the memory cell array responsive to the clock signal wherein the clock signal is applied to a clock input of each of the input buffers,
• a plurality of variable delay circuits wherein each variable delay circuit is coupled between the clock signal generator and a respective one of the data input/output buffers wherein each of the variable delay circuits is configured to provide one of a plurality of different time delays for the clock signal, and
• a delay controller coupled to each of the variable delay circuits wherein the delay controller is configured to select a respective delay to be provided by each of the variable delay circuits;
• and
• a memory controller coupled to the integrated circuit memory device wherein the memory controller is configured to transmit data to the plurality of input/output pads during write operations and to receive data from the plurality or input/output pads during read operations.

A method of operating an integrated circuit memory device including a memory cell array having a plurality of memory cells and a plurality of data input/output buffers coupled between respective data input/output pads and the memory cell array, the method comprising:

• generating a clock signal;
• during a first read/write operation, providing a first set of time delays for the clock signal at the input/output buffers so that different time delays are provided for the clock signal received by at least two of the input/output buffers;
• during the first read/write operation, communicating data between a memory controller and the memory cell array while providing the first set of time delays for the clock signal at the input/output buffers;
• during a second read/write operation, providing a second set of time delays for the clock signal at the input/output buffers so that different time delays are provided for the clock signal received by at least two of the input/output buffers, wherein the first and second sets of time delays are different;
• and
• during the second read/write operation, communicating data between the memory controller and the memory cell array while providing the second set of time delays for the clock signal at the input/output buffers.