Symmetrically operating single-ended input buffer devices and methods

A digital device comprising:

• a memory array from which data are read and to which data are written;
• a data path extending between a plurality of externally accessible data bus terminals and the memory array for coupling write data signals from the externally accessible data bus terminals to the memory array and read data signals from the memory array to the externally accessible data bus terminals;
• and
• a plurality of buffers coupled to one of the externally accessible terminals through which at least one of a command signals, address signals, or write data signals are coupled, at least one of the buffers comprising:
• a first amplifier circuit and a second amplifier circuit coupled in parallel to the first amplifier circuit, the second amplifier circuit have a topology that is complementary to the topology of the first amplifier circuit, each of the amplifier circuits comprising:
• an output node;
• a first transistor having a first terminal adapted to receive a first input signal;
• and
• a second transistor having a second terminal, capacitively coupled to the first terminal of the first transistor to provide a portion of the first input signal to the second transistor in a manner such that the drive strength of the amplifier circuit is adjusted as an output signal is generated at the output node.

A method of generating an output signal by a differential amplifier, comprising:

• receiving a first input signal that transitions;
• receiving a second input signal, the second input signal being a reference voltage having a relatively constant magnitude;
• and
• capacitively coupling a portion of the first input signal to a node of the differential amplifier that would transition in the same direction as a transition of the input signal responsive to a transition of the second input signal in a direction opposite the direction that the first input signal transitions.

A method of buffering an output signal comprising:

• receiving a first input signal at a first input node;
• receiving a second input signal at a second input node, the second input signal maintaining a constant voltage level;
• generating the output signal responsive to receiving the first input signal as the first input signal transitions;
• mimicking the transition of the first input signal in the opposite direction at the second input node;
• and
• generating the output signal at a faster rate responsive to the first input signal transitioning and mimicking the transition of the first input signal in the opposite direction at the second input node.