Nonvolatile memory device storing data based on change in transistor characteristics

A nonvolatile memory device, comprising:

• a pair of NMOS transistors;
• and
• a control circuit configured to operate in a store mode to apply to a first one of the NMOS transistors potentials that cause an PBTI degradation purposefully and to apply to a second one of the NMOS transistors potentials that cause no PBTI degradation while causing substantially no current to flow between a source node and a drain node of said first one of the NMOS transistors, and to operate in a recall mode to set gate nodes of the NMOS transistors to a common potential to detect a difference in the PBTI degradation between said NMOS transistors,
• wherein the gate node of said first one of the NMOS transistors is coupled to the drain node of said second one of the NMOS transistors, and the gate node of said second one of the NMOS transistors is coupled to the drain node of said first one of the NMOS transistors.

A nonvolatile memory device,

• comprising:
• a plurality of word lines;
• a plurality of bit line pairs;
• a memory cell array including a plurality of memory cells arranged in a matrix, one of said memory cells coupled to one of said bit line pairs that includes a first bit line and a second bit line, said one of said memory cells including:
• a latch having a first node and a second node configured such that a potential of the first node is inverse to a potential of the second node;
• a first PMOS transistor having one of source/drain nodes thereof coupled to the first node of said latch;
• a second PMOS transistor having one of source/drain nodes thereof coupled to the second node of said latch;
• a third transistor having a gate thereof coupled to one of said word lines and source/drain nodes thereof coupled to the first node and the first bit line, respectively;
• a fourth transistor having a gate thereof coupled to said one of said word lines and source/drain nodes thereof coupled to the second node and the second bit line, respectively;
• and
• a control circuit configured to operate in a store mode to apply to, the first PMOS transistor, potentials that cause an NBTI degradation purposefully, and to apply to, the second PMOS transistor, potentials that cause no NBTI degradation while causing no current to flow between the source/drain nodes of the first PMOS transistor, and to operate in a recall mode to set gate nodes of the first and second PMOS transistors to a common potential such as to cause said latch to detect a difference in the NBTI degradation between said first PMOS transistor and said second PMOS transistor,
• wherein the gate node of said first PMOS transistor as coupled to said second node of the latch, and the gate node of said second PMOS transistor is coupled to said first node of the latch.

A nonvolatile memory device, comprising:

• a plurality of word lines;
• a plurality of bit line pairs;
• a memory cell array including a plurality of memory cells arranged in a matrix, one of said memory cells coupled to one of said bit line pairs that includes a first bit line and a second bit line, said one of said memory cells including:
• a latch having a first node and a second node configured such that a potential of the first node is inverse to a potential of the second node;
• a first NMOS transistor having one of source/drain nodes thereof coupled to the first node of said latch;
• a second NMOS transistor having one of source/drain nodes thereof coupled to the second node of said latch;
• a third transistor having a gate thereof coupled to one of said word lines and source/drain nodes thereof coupled to the first node and the first bit line, respectively;
• a fourth transistor having a gate thereof coupled to said one of said word lines and source/drain nodes thereof coupled to the second node and the second bit line, respectively;
• and
• a control circuit configured to operate in a store mode to apply to, the first NMOS transistor, potentials that cause a PBTI degradation purposefully, and to apply to, the second NMOS transistor, potentials that cause no PBTI degradation while causing no current to flow between the source/drain nodes of the first NMOS transistor, and to operate in a recall mode to set gate nodes of the first and second NMOS transistors to a common potential such as to cause said latch to detect a difference in the PBTI degradation between said first NMOS transistor and said second NMOS transistor,
• wherein the gate node of said first NMOS transistor is coupled to said second node of the latch, and the gate node of said second NMOS transistor is coupled to said first node of the latch, said first node of the latch being at the first potential.