Systems and methods for discrete channel decoding of LDPC codes for flash memory
AssigneeIntel Corporation
InventorAlexander Kozlov
Life of this patent
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Abstract
Embodiments include systems and methods for soft encoding and decoding of data for flash memories using Log-Likelihood Ratios (LLRs). The LLRs are computed from statistics determined by observation of flash memory over time. In some embodiments, the write, retention and read transition probabilities are computed based on the observed statistics. These probabilities are used to compute the LLRs. During a read operation, a device reads the voltage of a cell of the flash memory. The level of the output is determined from the voltage. The level determines which LLRs to compute and transmit to a soft decoder.
Claims15
A method for determining data of a multi-level cell flash memory, comprising:
- reading a cell of the memory to determine a voltage level of the cell;
- determining a soft value of each bit of a group of bits corresponding to the level;
- wherein a soft value is determined from a priori information about the memory;
- and
- decoding the soft values to determine read values of the data.
A multi-level cell flash memory system for writing, storing and reading data, comprising:
- an encoder to encode data received for writing to the memory;
- a flash memory to receive data from the encoder and to store data and to make data available to be read by an external device, wherein a cell of the flash memory outputs a voltage level that is interpreted by an LLR calculator to be the closest one of four voltage levels of the cell;
- a Log-Likelihood Ratio (LLR) calculator to output a calculated LLR value of each bit of the most and least significant bits corresponding to the interpreted voltage level;
- and
- a decoder to decode the LLR values received from the calculator to determine read values of the memory system.
Dependencies are inferred from the claim text.