Nand type memory and programming method thereof
AssigneeMacronix International Co., Ltd.
InventorsWen-Chiao Ho, Chin-Hung Chang, Kuen-Long Chang, Chun-Hsiung Hung
Life of this patent
Estimating the term…
Abstract
A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.
Claims12
A memory, comprising
- a plurality of memory regions having a plurality of multilevel cells, each memory region comprising:
- a first bit line coupled to a first column of the multi-level cells;
- a second bit line coupled to a second column of the multi-level cells;
- a data buffer, coupled to the first bit line and the second bit line, for storing data to be programmed into the multi-level cells;
- and
- a protecting unit, coupled to the first bit line, the second bit line and the data buffer, for preventing a programming error.
A method of programming a memory, which comprises a plurality of memory regions each comprising a first bit line, a second bit line, a data buffer and a protecting unit, wherein the first bit line is coupled to a first column of multi-level cells, the second bit line is coupled to a second column of multi-level cells, the data buffer is coupled to the first bit line and the second bit line and is for storing data to be programmed into the multi-level cells, and the protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error, the programming method comprising the steps of:
- (a) respectively inputting corresponding data to the data buffers;
- (b) programming the data corresponding to the nth phase into the targeted multi-level cells, wherein n is a positive integer;
- (c) judging whether the targeted multi-level cells pass a programming verification process or not according to an nth programming verification voltage;
- (d) modifying data corresponding to an (n+1)th phase to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass the programming verification process;
- and
- (e) repeating steps (b) to (d) until n is equal to a maximum, wherein the step (d) is not performed when n is equal to the maximum,
- wherein programming operations of each of the phases are the same.
Dependencies are inferred from the claim text.