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US 2009/0154227 A1Published application
Integrated circuit including diode memory cells
AssigneeQimonda North America Corp.
InventorsJan Boris Philipp, Thomas Happ
Life of this patent
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Abstract
The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
Claims29
An integrated circuit comprising:
- a transistor;
- a contact coupled to the transistor;
- a first diode resistivity changing material memory cell coupled to the contact;
- and
- a second diode resistivity changing material memory cell coupled to the contact,
- wherein the second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
3 more elements
A system comprising:
- a host;
- and
- a memory device communicatively coupled to the host, the memory device comprising:
- an access transistor formed in a substrate;
- a vertical contact coupled to the transistor;
- a first diode resistive memory cell coupled to the vertical contact;
- and
- a second diode resistive memory cell coupled to the vertical contact,
- wherein the second diode resistive memory cell is located above the first diode resistive memory cell.
6 more elements
A memory comprising:
- a first diode;
- a first phase change element coupled to the first diode;
- a second diode;
- a second phase change element coupled to the second diode;
- and
- means for accessing the first phase change element and the second phase change element,
- wherein the second diode and the second phase change element are stacked over the first diode and the first phase change element.
4 more elements
A method for fabricating an integrated circuit, the method comprising:
- providing a preprocessed wafer including a transistor;
- fabricating a first diode resistive memory cell coupled to the transistor;
- fabricating a first bit line coupled to the first diode resistive memory cell;
- fabricating a vertical contact coupled to the transistor;
- fabricating a second diode resistive memory cell coupled to the vertical contact above the first diode resistive memory cell;
- and
- fabricating a second bit line coupled to the second diode resistive memory cell.
4 more elements
A method for fabricating an integrated circuit, the method comprising:
- providing a preprocessed wafer including a transistor and a first contact coupled to the transistor;
- forming a first metal pad contacting the first contact;
- depositing first dielectric material over exposed portions of the preprocessed wafer and the first metal pad;
- etching a first opening in the first dielectric material to expose a first portion of the first metal pad;
- fabricating a first diode in the first opening;
- depositing a first electrode material over the first diode in the first opening to provide a first electrode;
- depositing first phase change material over the first electrode;
- depositing second electrode material over the first phase change material;
- etching the second electrode material and the first phase change material to provide a second electrode and a first phase change material storage location;
- fabricating a bit line electrically coupled to the second electrode;
- depositing second dielectric material over exposed portions of the first dielectric material, the bit line, the second electrode, and the phase change material storage location;
- etching a second opening in the second dielectric material and the first dielectric material to expose a second portion of the first metal pad;
- depositing a contact material into the second opening to provide a second contact;
- and
- forming a second metal pad contacting the second contact.
12 more elements
Dependencies are inferred from the claim text.