Impedance compensated esd circuit for protection for high-speed interfaces and method of using the same
AssigneeSemiconductor Components Industries, LLC
InventorsJeffrey C. Dunnihoo, Richard Kimoto
Life of this patent
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Abstract
The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.
Claims10
A system for transmitting a signal and discharging an ESD event pulse associated with an ESD event to ground to protect a device under protection comprising:
- a printed circuit board having a PCB trace line that transmits the signal, the PCB trace line being formed of first and second line portions that are electrically isolated from one another;
- and
- an electrostatic discharge protection device mounted on the printed circuit board to protect the device under protection from the ESD event and for transmitting the signal from the first line portion to the second line portion, the electrostatic discharge protection device including device parasitics that have an inductance/capacitance ratio that match a PCB trace inductance/capacitance ratio, the electrostatic discharge protection device further including:
- an integrated semiconductor, the integrated semiconductor including:
- an input pad adapted for electrical coupling to the first line portion of the printed circuit board, that receives the signal and the ESD event pulse associated with the ESD event;
- an output pad adapted for electrical coupling to the second line portion of the printed circuit board;
- and
- an electrostatic discharge circuit connected between the input pad and the output pad, the electrostatic discharge circuit providing an electrical path for the signal from the input pad to the output pad and dissipating the ESD event pulse by providing a path to the ground.
A method of providing an impedance compensated ESD circuit for protection for high-speed interfaces comprising the steps of:
- determining a Lo/Co characteristic impedance ratio of PCB traces on which the ESD circuit will be mounted;
- and
- providing the impedance compensated ESD circuit having determined parasitics so that an L/C characteristic impedance ratio of the impedance compensated ESD circuit device is compensated to match the Lo/Co characteristic impedance ratio of the PCB traces.
Dependencies are inferred from the claim text.