Ink ejection device including a silicon chip having a heater stack positioned over a corresponding power transistor
AssigneeLexmark International, Inc.
InventorsYimin Guan, Kristi Maggard Rowe, Timothy Lowell Strunk, Carl Edmond Sullivan
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Abstract
A silicon chip has a plurality of inkjetting structures. Each ink jetting structure of the plurality of ink jetting structures includes a heater stack having an electrical heater element. A power transistor is electrically connected to the electrical heater element. A planarization layer is interposed between the power transistor and the heater stack. The planarization layer has a planar base surface on which the heater stack is formed.
Claims20
A silicon chip having a plurality of ink jetting structures, each ink jetting structure of said plurality of ink jetting structures comprising:
- a heater stack having an electrical heater element;
- a power transistor electrically connected to said electrical heater element;
- and
- a planarization layer interposed between said power transistor and said heater stack, said planarization layer having a planar base surface on which said heater stack is formed.
The silicon chip of claim I, wherein said planarization layer is formed on a dielectric material.
An ink ejection device, comprising:
- a nozzle plate having a plurality of nozzle holes;
- and
- a silicon chip having a plurality of inkjetting structures respectively associated with said plurality of nozzle holes, each ink jetting structure of said plurality of ink jetting structures including:
- a heater stack having an electrical heater element;
- a power transistor electrically connected to said electrical heater element;
- and
- a planarization layer interposed between said power transistor and said heater stack, said planarization layer having a planar base surface on which said heater stack is formed.
A method for fabricating a silicon chip for use in an ink ejection device, comprising:
- forming a plurality of power transistors on a die of semiconductor material;
- forming a planarization layer over said plurality of power transistors;
- smoothing said planarization layer to form a planar base surface;
- and
- forming a plurality of heater stacks on said planar base surface, with each heater stack of said plurality of heater stacks being positioned directly over and electrically connected to a respective power transistor of said plurality of power transistors.
Dependencies are inferred from the claim text.