Time interpolation flash adc having automatic feedback calibration
AssigneeNXP B.V.
InventorsMikko WALTARI, Costantino Pala
Life of this patent
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Abstract
An input signal is compared to 2N−1 reference voltages to generate 2N−1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.
Claims15
A flash analog-to-digital converter, comprising:
- a flash comparator portion to compare an input signal to 2N−1 reference voltages and to generate 2N−1 corresponding binary valued comparison signals, wherein adjacent comparison signals represent a given least significant bit quantization level;
- a time interpolating encoder to detect a difference in arrival time between a first comparison signal and a second comparison signal from among the binary valued comparison signals and, based on the difference, to generate a voltage interpolation signal capable of encoding a plurality of bins within the given least significant bit quantization level, and capable of identifying which of the bins corresponds to the input signal, wherein the time interpolating decoder includes at least one variable delay unit to delay, based on a feedback control signal, at least one of the first comparison signal and the second comparison signal prior to detecting said difference;
- a decoder to generate M-bit output data representing an M-bit quantization of the input signal, wherein M is an integer greater than N, based on the binary valued comparison signals and the voltage interpolation signal;
- a feedback control signal generator to generate the feedback control signal, the generator including a code density detector to detect a non-uniformity of a code density of the M-bit output data, wherein the generator generates the control signal based on the detecting.
A flash analog-to-digital converting method, comprising:
- comparing an input signal to 2N−1 reference voltages;
- generating 2N−1 corresponding binary valued comparison signals, based on the comparing, wherein adjacent comparison signals represent a given least significant bit quantization level;
- detecting a difference in arrival time between a first comparison signal and a second comparison signal from among the binary valued comparison signals and, based on the difference, generating a first-to-arrive signal, wherein the detecting includes delaying at least one of the first comparison signal and the second comparison signal prior to detecting said difference;
- generating a voltage interpolation signal capable of encoding a plurality of bins within the given least significant bit quantization level, and capable of identifying which of the bins corresponds to the input signal, said generating based on said first-to-arrive signal;
- generating an M-bit output data representing an M-bit quantization of the input signal, based on the binary valued comparison signals and the voltage interpolation signal;
- detecting a non-uniformity of a code density of the M-bit output data and generating a corresponding uniformity error data;
- generating a feedback control signal based on the uniformity error data;
- and
- varying said delaying based on said feedback control signal.
Dependencies are inferred from the claim text.