Digital-to-analogue converter

Abstract

A digital-to-analogue conversion arrangement is disclosed which includes first and second groups of the same number of bi-directional bufferless digital-to-analogue converters. The output of at least one converter in each group is connected to a respective capacitive load (CLOAD, CLOAD′). During a calibration phase of operation the converter inputs receive first and second different codes representing the same output level. The arrangement also includes a respective switched capacitor network connected to each converter output, a comparator for comparing the output voltages of the first and second groups, and a control circuit. The control circuit controls the capacitor networks in response to the comparator so as to make the output voltages of the first and second groups substantially equal.

Dependencies are inferred from the claim text.