Phase locked loop circuit performing two point modulation and gain calibration method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsHwa Yeal Yu, Dong Jin Keum
Life of this patent
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AssigneeSamsung Electronics Co., Ltd.
InventorsHwa Yeal Yu, Dong Jin Keum
Estimating the term…
A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.
A PLL circuit for two point modulation, the PLL circuit comprising:
A method of calibrating a gain of a PLL circuit during a gain calibrating operation using a first loop filter having a bandwidth wider than a bandwidth of a second loop filter operated during a normal operation, the method comprising:
A PLL circuit for two point modulation, the PLL circuit comprising:
Dependencies are inferred from the claim text.