US 2009/0153244 A1 · LOW NOISE AND LOW INPUT CAPACITANCE DIFFERENTIAL MDS LNA

Abstract

A differential low noise amplifier (LNA) involves two main amplifying transistors biased in saturation, and two cancel transistors biased in sub-threshold. In one example, the gates of the cancel transistors are coupled to the drains of main transistors, in a symmetrical and cross-coupled fashion. The main transistors are source degenerated. Because the gates of cancel transistors are not coupled to the differential input leads of the LNA, the input capacitance of the LNA is reduced. Noise introduced into the LNA output due to the cancel transistors being biased in the sub-threshold region is reduced because there are two stages. The first stage involves the main transistors, and the second stage involves the cancel transistors. By increasing the gain of the first stage and decreasing the gain of the second stage, overall LNA gain is maintained while reducing the noise that the sub-threshold biased transistors contribute to the LNA output.

Claims20

Dependent claims

An amplifier having a first differential input node and a second differential input node, the amplifier comprising:

a first transistor biased in the saturation region, wherein a gate of the first transistor is coupled to the first differential input node;
a second transistor biased in the saturation region, wherein a gate of the second transistor is coupled to the second differential input node;
a third transistor biased in the sub-threshold region, the third transistor having a gate that is capacitively coupled to a drain of the second transistor, wherein a first cancel signal on a drain of the third transistor cancels at least a part of a first distortion signal generated by the first transistor;
and
a fourth transistor biased in the sub-threshold region, the fourth transistor having a gate that is capacitively coupled to a drain of the first transistor, wherein a second cancel signal on a drain of the fourth transistor cancels at least a part of a second distortion signal generated by the second transistor.

2 more elements

An amplifier having a first differential input node, a second differential input node, a first differential output node, and a second differential output node, the amplifier comprising:

a first transistor biased in the saturation region, wherein a gate of the first transistor is coupled to the first differential input node;
a second transistor biased in the saturation region, wherein a gate of the second transistor is coupled to the second differential input node;
a third transistor biased in the sub-threshold region, wherein a first cancel signal on a drain of the third transistor cancels at least a portion of a first distortion signal generated by the first transistor;
a fourth transistor biased in the sub-threshold region, wherein a second cancel signal on a drain of the fourth transistor cancels at least a portion of a second distortion signal generated by the second transistor;
a fifth transistor having a source and a drain, wherein the source of the fifth transistor is coupled to a drain of the first transistor, and wherein the drain of the fifth transistor is coupled to the first differential output node and is also capacitively coupled to a gate of the fourth transistor;
and
a sixth transistor having a source and a drain, wherein the source of the sixth transistor is coupled to a drain of the second transistor, and wherein the drain of the sixth transistor is coupled to the second differential output node and is also capacitively coupled to a gate of the third transistor.

4 more elements

A method comprising:

(a) using a first transistor biased in the saturation region to amplify a first input signal received on a first differential input node and to generate an amplified version of the first input signal, wherein the first transistor also generates a first distortion signal;
(b) using a second transistor biased in the saturation region to amplify a second input signal received on a second differential input node and to generate an amplified version of the second input signal, wherein the second transistor also generates a second distortion signal;
(c) supplying the amplified version of the second input signal to a third transistor so that the third transistor generates a first cancel signal, wherein the third transistor is biased in the sub-threshold region;
(d) using the first cancel signal to cancel at least a part of the first distortion signal;
(e) supplying the amplified version of the first input signal to a fourth transistor so that the fourth transistor generates a second cancel signal, wherein the fourth transistor is biased in the sub-threshold region;
and
(f) using the second cancel signal to cancel at least a part of the second distortion signal.

4 more elements

Dependencies are inferred from the claim text.

Low noise and low input capacitance differential mds lna

Life of this patent

Low noise and low input capacitance differential mds lna

Life of this patent

Abstract

Claims20