US 2009/0153210 A1 · Maintaining output I/O signals within an integrated circuit with multiple power domains

Abstract

An integrated circuit is provided with a power domain PD0, PD1, PD2, PD3 which can be selectively powered-up or powered-down. An output circuitry 8 serving to buffer a signal 12 generated by the core circuitry 10 within such a power domain has its own output power supply voltage IOVdd. An adaptive voltage sensing circuit 24 senses when the core power supply voltage to the core circuitry 10 falls below a threshold level and generates a voltage-low signal. If output signal retention has been preselected to be active for the output signal concerned, then the output circuitry 8 responds to the voltage-low signal by maintaining the output signal state (output signal driven low, output signal driven high or output signal in a high impedance drive state). The retention mode is preselected by a on-shot pulse with its value stored within a mode latch 24 indicating whether or not retention is required. Thus, when the adapted voltage sensing circuitry 24 itself senses the voltage level for the core circuitry 10 falling below the threshold, it activates the retention operation.

Claims25

Dependent claims

An integrated circuit comprising:

core circuitry powered by core power supply circuitry at a core power supply voltage, said core circuitry having a core output;
output circuitry powered by output power supply circuitry, said output power supply circuitry being controlled separately from said core power supply circuitry, and coupled to said core circuitry to receive a core signal from said core output, said output circuitry being at least partially dependent upon said core signal to generate an output signal having one of a plurality of different output states;
voltage sensing circuitry coupled to said core power supply circuitry and responsive to sensing of said core power supply voltage falling below a threshold level to assert a voltage-low signal;
a mode signal store responsive to a retention preselecting signal to store a mode signal indicative of whether or not signal retention is preselected;
wherein
said output circuitry is responsive to asserting of said voltage-low signal when said mode signal indicates retention is preselected to maintain a current output state of said output signal independently of said core signal.

3 more elements

A method of operating an integrated circuit, said method comprising the steps of:

powering core circuitry at a core power supply voltage using core power supply circuitry, said core circuitry having a core output;
powering output circuitry using output power supply circuitry, said output power supply circuitry being controlled separately from said core power supply circuitry;
receiving with said output circuitry a core signal from said core output;
in at least partial dependence upon said core signal, generating with said output circuitry an output signal having one of a plurality of different output states;
sensing said core power supply voltage with sensing circuitry coupled to said core power supply circuitry;
asserting a voltage-low signal voltage in response to sensing of said core power supply voltage falling below a threshold level;
in response to a retention preselecting signal, storing in a mode signal store a mode signal indicative of whether or not signal retention is preselected;
and
in response to asserting of said voltage-low signal when said mode signal indicates retention is preselected, maintaining a current output state of said output signal independently of said core signal.

6 more elements

Dependencies are inferred from the claim text.

Maintaining output I/O signals within an integrated circuit with multiple power domains

Life of this patent

Maintaining output I/O signals within an integrated circuit with multiple power domains

Life of this patent

Abstract

Claims25