Pll circuit

A PLL circuit comprising a loop filter for smoothing a current which is pushed and pulled in accordance with a phase difference between a reference clock signal and a feedback clock signal, and a voltage-current converting circuit for converting an output voltage of the loop filter into a current, characterized by comprising:

• a current source;
• an initialization switch which, when receiving an initialization signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the initialization switch being inserted in series to an input terminal of the loop filter and the current source;
• and
• a reset switch which, when receiving a reset signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the reset switch being provided between an input terminal of the voltage-current converting circuit and a ground node;
• a deadlock detecting circuit for detecting that the PLL circuit is in a deadlock state;
• and
• a control section for outputting the reset signal when the deadlock state detected by the deadlock detecting circuit continues for a predetermined time or more, and outputting the initialization signal during start-up of the PLL circuit and following the outputting of the reset signal.

A PLL circuit comprising a phase detector for comparing a phase difference between a reference clock signal and a feedback clock signal, a loop filter for smoothing a current which is pushed and pulled in accordance with a result of phase comparison by the phase detector, and a voltage-current converting circuit for converting an output voltage of the loop filter into a current, characterized by comprising:

• a clock generating circuit for generating a dummy clock signal having a phase difference with reference to the reference clock signal;
• and
• a selector for inputting the dummy clock signal to the phase detector when an initialization signal is at a predetermined logic level, and the feedback clock signal to the phase detector when the initialization signal is at a logic level other than the predetermined logic level;
• a reset switch which, when receiving a reset signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the reset switch being provided between an input terminal of the voltage-current converting circuit and a ground node;
• a deadlock detecting circuit for detecting that the PLL circuit is in a deadlock state;
• and
• a control section for outputting the reset signal when the deadlock state detected by the deadlock detecting circuit continues for a predetermined time or more, and outputting the initialization signal having the predetermined logic level during start-up of the PLL circuit and following the outputting of the reset signal.