Differential multiphase frequency divider

A multiphase divider, comprising:

• a plurality of differential latches each having differential D-inputs (dp and dn), differential clock inputs (cp and cn), and differential Q-outputs (qp and qn), wherein said Q-outputs are connected to the D-inputs of a next latch stage, and a last differential Q-output is returned to a first D-input, and wherein each latch comprises a differential pair of clock transistors for cp and cn, a differential pair of data transistors for dp and dn connected in totempole respectively with the differential pair of clock transistors, and a differential pair of cross-connected Q-output transistors for qp and qn connected in totempole respectively with the differential pairs of clock and data transistors;
• a differential divider clock input (ckip and ckin) connected to said differential clock inputs (cp and cn);
• a plurality of multiphase divider outputs respectively taken in parallel from said differential Q-outputs (qp and qn) of each one of the plurality of differential latches;
• if the number of differential latches in the plurality is an even number, then said last differential Q-output is returned to a first D-input and cross-connected qp to dn, and qn to dp, and said differential clock inputs (cp and cn) of each differential latch are connected together, and then to alternating ones of the differential divider clock inputs (ckip and ckin);
• and if the number of differential latches in the plurality is an odd number, then said last differential Q-output is returned to a first D-input and straight-connected qp to dp, and qn to dn, and said differential clock inputs (cp and cn) of each differential latch are connected in parallel to corresponding ones of the differential divider clock inputs (ckip and ckin);
• wherein, the number of differential latches in the plurality is equal to the integer divisor of the divider, and equal to the number of phases produced.

A divide-by-four, four-phase multiphase divider, comprising:

• a first differential latch having differential D-inputs (dp and dn), differential clock inputs (cp and cn) connected together and to a divider clock input (ckip), and differential Q-outputs (qp and qn) with a first phase (p1p and p1n);
• a second differential latch having differential D-inputs (dp and dn) connected to said first phase (p1p and p1n), differential clock inputs (cp and cn) connected together and to a divider clock complement input (ckin), and differential Q-outputs (qp and qn) with a second phase (p2p and p2n);
• a third differential latch having differential D-inputs (dp and dn) connected to said second phase (p2p and p2n), differential clock inputs (cp and cn) connected together and to said divider clock input (ckip), and differential Q-outputs (qp and qn) with a third phase (p3p and p3n);
• and a fourth differential latch having differential D-inputs (dp and dn) connected to said third phase (p3p and p3n), differential clock inputs (cp and cn) connected together and to said divider clock complement input (ckin), and differential Q-outputs (qp and qn) with a fourth phase (p4p and p4n) cross-connected back to the D-inputs of the first differential latch;
• wherein, a frequency differentially applied to said divider clock input (ckip) and complement input (ckin) will be divided by four and output in four equally spaced phases at respective Q-outputs.

A divide-by-five, five-phase multiphase divider, comprising:

• a first differential latch having differential D-inputs (dp and dn), differential clock inputs (cp and cn) respectively connected to a divider clock input (ckip) and a complement input (ckin), and differential Q-outputs (qp and qn) with a first phase (p1p and p1n);
• a second differential latch having differential D-inputs (dp and dn) connected to said first phase (p1p and p1n), differential clock inputs (cp and cn) respectively connected to said divider clock input (ckip) and said complement input (ckin), and differential Q-outputs (qp and qn) with a second phase (p2p and p2n);
• a third differential latch having differential D-inputs (dp and dn) connected to said second phase (p2p and p2n), differential clock inputs (cp and cn) respectively connected to said divider clock input (ckip) and said complement input (ckin), and differential Q-outputs (qp and qn) with a third phase (p3p and p3n);
• a fourth differential latch having differential D-inputs (dp and dn) connected to said third phase (p3p and p3n), differential clock inputs (cp and cn) respectively connected to said divider clock input (ckip) and said complement input (ckin), and differential Q-outputs (qp and qn) with a fourth phase (p4p and p4n);
• and a fifth differential latch having differential D-inputs (dp and dn) connected to said fourth phase (p4p and p4n), differential clock inputs (cp and cn) respectively connected to said divider clock input (ckip) and said complement input (ckin), and differential Q-outputs (qp and qn) with a fifth phase (p5p and p5n) straight-connected back to the respective D-inputs of the first differential latch;
• wherein, a frequency differentially applied to said divider clock input (ckip) and complement input (ckin) will be divided by five and output in five equally spaced phases at respective Q-outputs.