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US 2009/0153191 A1Published application
Pre-driver logic
AssigneeMicron Technology, Inc.
InventorsWILLIAM CHAD WALDROP, DANIEL PENNEY
Life of this patent
Estimating the term…
Abstract
At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.
Claims25
A system, comprising:
- driver logic capable of driving a device;
- pre-driver logic coupled to the driver logic and that drives the driver logic;
- wherein, if the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal;
- wherein, if the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal;
- wherein, if the third transistor is not activated, the pre-driver logic provides said output signal.
2 more elements
Pre-driver logic, comprising:
- a first transistor combination;
- a second transistor combination coupled to the first transistor combination;
- and
- a separate transistor coupled to the first transistor combination;
- wherein, when a first type of input signal is received, a transistor in the first transistor combination causes the second transistor combination to drive an output signal to a voltage level;
- wherein, when a different type of input signal is received, another transistor in the first transistor combination and said separate transistor together cause the second transistor combination to drive the output signal to a different voltage level;
- wherein, when the output signal is driven to said different voltage level, the separate transistor is inactivated.
4 more elements
A system, comprising:
- a first transistor combination;
- a second transistor combination coupled to the first transistor combination;
- and
- a separate transistor coupled to the first and second transistor combinations;
- wherein, when an input signal is received, a first type of transistor in the first transistor combination is activated, thereby activating another type of transistor in the second transistor combination and resulting in an output signal that corresponds to the input signal;
- wherein, when a different input signal is received, a transistor of said first type in the second transistor combination is activated, thereby activating another transistor of said second type in the first transistor combination, thereby activating said separate transistor and causing said another type of transistor in the second transistor combination to be inactivated, thereby causing the output signal to correspond to the different input signal.
3 more elements
A system, comprising:
- a NAND gate;
- a p-channel transistor coupled to the NAND gate via a level shifter, said p-channel transistor also coupled to an inverter at a first node, the inverter coupled to the NAND gate;
- a first transistor combination comprising a first p-channel transistor and a first n-channel transistor, the first p-channel transistor and the first n-channel transistor coupled at said first node;
- a second transistor combination comprising a second p-channel transistor and a second n-channel transistor, an input to the second p-channel transistor coupled to the first node, an input to the second n-channel transistor coupled to an input to the first n-channel transistor at a second node via an inverter, said second node coupled to an input of the NAND gate via another inverter, the second p-channel and second n-channel transistors coupled via a third node that couples to an input to the first p-channel transistor.
1 more element
A system, comprising:
- means for receiving an input signal;
- means for activating, if the input signal is of a first type, an n-channel transistor of a first transistor combination, thereby activating a p-channel transistor of a second transistor combination and providing an output signal that is of said first type;
- means for activating, if the input signal if of a second type, a p-channel transistor of the first transistor combination and an independent transistor, thereby causing the p-channel transistor of the second transistor combination to be disabled and causing the output signal to be of said second type;
- means for de-activating, if said p-channel transistor of the second transistor combination is de-activated, the independent transistor.
1 more element
Dependencies are inferred from the claim text.