PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)

An intermediate level configuration unit for implementation in a field programmable gate array integrated circuit, wherein the intermediate level configuration unit is located between a high level configuration load unit and at least some of configurable cells that are dynamically configurable at runtime by other cells of the field programmable gate array integrated circuit, the intermediate level configuration unit comprising:

• memory for receiving configuration strings from the high level configuration load unit;
• and
• a controller including at least one pointer into the memory for selecting from the memory a configuration string to be dynamically loaded into the at least some of the configurable cells.

A field programmable gate array integrated circuit comprising:

• a high level configuration load unit;
• and
• a plurality of configurable cells, at least some of the configurable cells being dynamically configurable at runtime by other cells of the plurality of configurable cells, and at least some of the configurable cells being adapted to operate as local memory cells.

A runtime reconfigurable processing integrated circuit comprising:

• a plurality of cells configurable by a high level configuration load unit, at least some of the configurable cells being dynamically configurable at runtime by others of the configurable cells;
• wherein at least one intermediate level configuration unit of the runtime reconfigurable processing integrated circuit is located between the high level configuration load unit and the at least some of the configurable cells, and is adapted for configuring the at least some of the configurable cells.

An intermediate level configuration unit for implementation in a runtime reconfigurable processing integrated circuit, wherein the intermediate level configuration unit is located between a high level configuration load unit and at least some of configurable cells that are dynamically configurable at runtime by other cells of the runtime reconfigurable processing integrated circuit, the intermediate level configuration unit comprising:

• memory for receiving configuration strings from the high level configuration load unit;
• and
• a controller including at least one pointer into the memory for selecting from the memory a configuration string to be dynamically loaded into the at least some of the configurable cells.