Output driver circuit with output preset circuit and controlling method thereof having lower power consumption
AssigneeMacronix International Co., Ltd.
InventorYunghsu Chen
Life of this patent
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Abstract
The configurations of an output preset circuit for an output driver circuit and the controlling methods thereof are provided. The proposed output preset circuit includes a latch generating an latch output signal and a pull-up circuit receiving an preset enable signal and the latch output signal, in which the pull-up circuit increases an output voltage of the output driver circuit from a ground level to a first level when the preset enable signal is at a low level and the latch output signal is at the high level.
Claims17
An output preset circuit for an output buffer, comprising:
- a latch having a first input terminal receiving a power on reset signal, a second input terminal receiving a voltage of the output buffer and an output terminal outputting a latch output signal;
- and
- an output preset device, comprising:
- a pull-up circuit receiving a preset enable signal and the latch output signal, wherein the pull-up circuit increases the voltage of the output buffer from a ground level to a first level when the preset enable signal is active and the latch output signal is at the high level;
- and
- a pull-low circuit receiving the preset enable signal and the latch output signal, wherein the pull-low circuit decreases the voltage of the output buffer from a power voltage level to a second level when the preset enable signal is active and the latch output signal is at the low level.
A controlling method for an output driver circuit, wherein the output driver circuit comprises an output load and an output preset circuit having a latch, and the latch generates an output signal, comprising the steps of:
- (a) activating a preset enable signal so as to preset a voltage of the output load to be one of a first level increased from a ground level and a second level decreased from a power voltage level;
- (b) increasing the voltage of the output load to a high level when the output signal of latch is at the high level;
- and
- (c) decreasing the voltage of the output load to a low level when the output signal of latch is at the low level.
Dependencies are inferred from the claim text.