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AssigneeElpida Memory, Inc.
InventorKayoko SHIBATA
Estimating the term…
A stacked semiconductor device is disclosed which is capable of conducting a test to determine whether or not there is continuity between an external terminal and a corresponding internal terminal in each chip, on an internal terminal-in each chip basis. The semiconductor device includes continuity test dedicated terminals for each chip, and continuity test elements each connected between an internal terminal in each chip and a continuity test dedicated terminal associated with the chip. A voltage is applied between an external terminal associated with an internal terminal whose connection status is to be checked and a continuity test dedicated terminal associated with a chip which includes the internal terminal such that a continuity test element associated with the internal terminal is rendered conductive. Thereafter, the value of current that flows through the continuity test element is measured to determine the connection status of the internal terminal.
A stacked semiconductor device comprising:
A stacked semiconductor device comprising:
A method of testing a connection status of a stacked semiconductor device comprising:
Dependencies are inferred from the claim text.