Simple and effective method to detect poly residues in locos process

A test structure for a semiconductor device, comprising:

• at least a portion of a semiconductor wafer;
• a metal oxide semiconductor (MOS) device comprising a source, a drain, and a transistor gate;
• a one time programmable floating gate transistor comprising a source, a drain, and a floating gate;
• a first probe contact electrically coupled with the source of the MOS device and the source of the floating gate transistor;
• a second probe contact electrically coupled with the drain of the MOS device;
• a third probe contact electrically coupled with the transistor gate of the MOS device;
• a fourth probe contact electrically coupled with the drain of the floating gate transistor;
• and
• a fifth probe contact electrically coupled with the semiconductor wafer.

A method for testing a semiconductor device, comprising:

• providing a test structure comprising a MOS transistor and a floating gate transistor;
• applying voltages to the MOS transistor which are sufficient to activate a functional MOS transistor;
• applying voltages to the MOS transistor which are not sufficient to activate a functional MOS transistor;
• applying voltages to the floating gate transistor which are not sufficient to activate a functional unprogrammed floating gate transistor;
• then
• applying voltages to the floating gate transistor which are sufficient to program a functional floating gate transistor;
• then
• applying voltages to the floating gate transistor which are sufficient to activate a functional programmed floating gate transistor.

A method used to test for residual conductive material on a semiconductor device resulting from an under etch of a conductive layer, comprising:

• providing at least one test structure comprising:
• a p-type metal oxide semiconductor (PMOS) transistor;
• a one time programmable (OTP) erasable programmable read-only memory (EPROM) comprising a source, a drain, a channel, and a floating gate;
• providing a back gate interposed between the OTP EPROM and the PMOS transistor;
• testing the PMOS transistor for functionality;
• if the PMOS transistor is not functional, failing the semiconductor device;
• if the PMOS transistor is functional, prior to programming the OTP EPROM, applying a first test voltage comprising applying about −1.0 V to the OTP EPROM drain and about 0.0 V to both the back gate and the OTP EPROM source;
• if a current through the OTP EPROM channel during application of the first test voltage is less than about 1.0 microamp (μA) or more than about 100 μA, failing the semiconductor device;
• if current through the OTP EPROM channel during application of the first test voltage is between about 1.0 μA and about 100 μA, programming the OTP EPROM;
• after programming the OTP EPROM, applying a second test voltage comprising about −1.0 V to the OTP EPROM drain and about 0.0 V to both the back gate and the OTP EPROM source;
• and
• if current through the OTP EPROM channel during application of the second voltage is less than about 10 μA or more than about 100 μA, failing the semiconductor device.