Hi-fix board, test tray, test handler, and method for manufacturing packaged chips

A hi-fix board comprising:

• test sockets to which packaged chips to be tested are connected;
• and
• a main frame in which the test sockets are arranged in a first area including at least one row and a second area including the other rows,
• wherein the number of test sockets disposed in each row of the second area in the main frame is greater than the number of test sockets in each row of the first area.

A test tray comprising:

• containing units containing packaged chips;
• and
• a tray frame in which the containing units are disposed in a first containing area forming at least one row and in a second containing area forming the other rows,
• wherein the containing units are disposed in the tray frame so as to contain the packaged chips, which are more than the packaged chips in each row of the first containing area, in each row of the second containing area.

A test handler comprising:

• a test tray including containing units containing packaged chips and a tray frame in which the containing units are disposed in at least one first containing area to contain the packaged chips in an a×b (where a and b are integers greater than 0) matrix and are disposed in at least one second containing area to contain the packaged chips in an c×d (where d is an integer greater than a and d is an integer greater than 0) matrix;
• a loading unit containing the packaged chips to be tested in the test tray located in a loading position;
• a chamber system adjusting the packaged chips to be tested in the test tray to a testing temperature, connecting the packaged chips adjusted to the testing temperature to a hi-fix board, and restoring the tested packaged chips to a normal temperature;
• an unloading unit disposed aside the loading unit so as to classify the tested packaged chips contained in the test tray located in an unloading position on the basis of the test result;
• and
• a transferring unit transferring the test tray among the loading position, the chamber system, and the unloading position.

A packaged chip manufacturing method comprising the steps of:

• preparing packaged chips to be tested;
• containing the prepared packaged chips in a test tray located at a loading position;
• adjusting the packaged chips contained in the test tray to a testing temperature;
• connecting the packaged chips contained in the test tray and adjusted to the testing temperature to a hi-fix board;
• restoring the tested packaged chips contained in the test tray to a normal temperature;
• and
• classifying the tested packaged chips contained in the test tray located at an unloading position on the basis of the test result,
• wherein the test tray includes containing units containing the packaged chips and a tray frame in which the containing units are disposed in at least one first containing area to contain the packaged chips in an a×b (where a and b are integers greater than 0) matrix and are disposed in at least one second containing area to contain the packaged chips in an c×d (where d is an integer greater than a and d is an integer greater than 0) matrix.